The present invention relates generally to a timing signal generating circuit and is preferably applicable, more particularly, to a driving circuit of a video display apparatus using a matrix drive system.
The following is a description of construction of a video display apparatus employing a matrix driving system, especially an active matrix type liquid crystal display device.
FIG. 16 is a schematic diagram illustrating a typical construction of the active matrix type liquid crystal display apparatus.
A liquid crystal display element 1201 which is an element for displaying picture images is disposed at each intersection between a signal line 1203 serving as an X-line and a gate line 1204 serving as a Y-line, and is connected to the X-line 1203 and the Y-line 1204. The X- and Y-lines 1203, 1204 are connected respectively to an X-line drive circuit 1206 and Y-line drive circuit 1207, and a timing at which timing signal generating circuits 1208, 1209 respectively constituting the drive circuits 1206, 1207 transmit electric signals, is thereby controlled.
FIG. 17 is a circuit block diagram showing one example of a shift register type timing signal generating circuit.
In this timing signal generating circuit, flip-flop circuits 1303 each consisting of an inverter 1302 and two pieces of loop-connected inverters 1301 each serve as one constructive unit of the shift register and are serially connected. Then, a timing input signal to the shift register is shifted stage by stage for every clock of each stage, thereby generating a timing output signal for controlling the timing of the X- and Y-lines 1203, 1204.
Note that symbols .phi. and /.phi. in the Figure represent clock signals, and the clocks .phi. and /.phi. are in a mutually inverted relationship (which is the same hereinbelow).
The video display element may involve the use of, in addition to the liquid crystal display element, discharge gases, fluorescent materials, light emitting diodes, light source tubes, electron beam fluorescent tubes, and magneto-electric driving type reflection display elements. In any display element, a display state is varied by the electric signals supplied to the X- and Y-lines corresponding to the timings, an arbitrary picture is thereby displayed on the screen.
As described above, the matrix drive system video display apparatus is capable of arbitrarily changing the display state on the screen by controlling the timings of transmitting the electric signals to the X- and Y-lines.
If this drive timing becomes defective, however, the display elements arrayed in matrix become uncontrollable, resulting in a linear or planar defective display on the screen. For example, in a shift register type timing control circuit, when the timing input signal to be transmitted to a next-stage shift register becomes defective, the display elements controlled by the shift registers subsequent thereto are all brought into a display defective state.
Further, the shift register type timing control circuit is constructed such that the supplied-from-outside signals such as the clock signals, the timing input signals (start pulses), etc. are connected directly to the respective elements within the circuit, and therefore extremely fragile against an electrostatic breakdown during a manufacturing process. In particular, this defect in terms of construction is the problem inherent in a drive circuit integral type video display apparatus in which a drive circuit is formed simultaneously with the display element, and this problem turns out an obstacle against enhancing a yield and a reliability of the video display apparatus as well as against decreasing costs for the display apparatus.
A first countermeasure to obviate the above problem entails an adoption of such a construction that the X- and Y-lines are respectively driven on both sides of the lines, and, if the drive circuit on one side falls into a breakdown, the drive circuit on the other side compensates it.
Proposed further as a second countermeasure is a construction wherein a decoder system for generating the timing output signals selectively corresponding to input coded numerical signals are applied to the timing signal generating circuit.
FIG. 18 is a circuit block diagram showing one example of the decoder type timing signal generating circuit. Unlike the sift register system in which the timing input signals are shifted stage by stage for every clock of each stage, each decoder circuit 1401 generates the timing output signal, and therefore the planar display defect as seen in the shift register type circuit hardly occur. Besides, there must be an advantage in which an operation of cutting off the defective line and repairing it can be more simplified than by the shift register type circuit.
Proposed also as a third countermeasure is such a construction that a preparatory shift register or decoder is previously included in the drive circuit.
FIG. 19 is a circuit block diagram showing a timing signal generating circuit including the preparatory shift register. FIG. 20 is a circuit block diagram illustrating a timing signal generating circuit including the preparatory decoder. Based on these constructions, if drive defects are caused on the shift register and the decoder, a shift register 1502 or a decoder 1505 troubled with the drive defect is disconnected from the line by a laser or the like. Then, a preparatory shift register 1501 or a preparatory decoder 1504 included therein is connected to a preparatory shift register connecting node 1503 or a preparatory decoder connecting node 1504 by use of a conductive material such as silver paste, etc., or by irradiation of laser beams.
A fourth countermeasure proposed may be a construction wherein k-trains (k is two or more) of shift registers operating at the same timing are disposed in parallel, and k-input NOR circuits are inserted between two stages (FIG. 21).
FIG. 21 is a circuit block diagram of a timing signal generating circuit constructed such that the k-trains of shift registers operating at the same timing are, as shown in FIG. 2, P.40, Vol.56 of the Sharp Corporation Technical Report, arranged in parallel, and the k-input NOR circuits are inserted at the interval of the plurality of stages of the shift registers. According to this construction, even if some of k-trains of shift registers 1601 fall into breakdown, a NOR circuit 1602 is capable of picking up and eliminating the defective timing input signal. Besides, even if incapable of picking up and eliminating the defective signal, a normal drive operation can be done by disconnecting the k-input NOR circuit from the shift register train with the defect occurred therein.
The following are problems inherent in the respective constructions of countermeasures given above.
According to the first countermeasure, i.e., the construction of respectively driving the X- and Y-lines on both sides of the lines and, if the drive circuit on one side falls into the breakdown, compensating it by the drive circuit on opposite side, this construction can not be adopted in principle when the lines are to be driven on both sides on account of a magnitude of the drive load. Further, even if the drive load is small enough to be drive on one side, there arises a necessity for electrically disconnecting the defective drive circuit from the matrix line, and hence there must be performed an operation of cutting off a part of the line by use of the laser, etc.
The second countermeasure, i.e., the decoder type timing signal generating circuit is based on the premise that the lines can be driven on one side, and the condition remains the same as requiring the operation of cutting off the defective portion by the laser.
The third counter measure, i.e., the construction of incorporating the preparatory shift register or decoder into the drive circuit, might need the operations of cutting off the defective portion by the laser and of connecting the preparatory circuit. Therefore, this counter measure is, it can not be said, realistic in terms of mass production because of the drive circuit repair process being complicated.
According to the fourth countermeasure, i.e., the construction of arranging in parallel the k-trains, over two trains, of shift registers operating at the same timing and inserting the k-input NOR circuits at the interval of the plurality of stages, if some defect happens in the shift register, and a judgement as to whether the defect is gets fixed on a High-side or a Low-side is different as the case may be. The defect getting fixed on the High-side might require the operation of disconnecting the line by use of the laser, etc.
Moreover, a problem pertaining to the above-described constructions as a whole may be concerned with a reliability of the drive circuit. If the timing signal generating circuit becomes defective during the use of the video display apparatus, the video display apparatus can not be continuously used without performing the repairing operation in the prior arts. Accordingly, especially in the drive circuit integral type video display apparatus, it is much importance in terms of enhancing the reliability of the display apparatus to construct the whole drive circuit in consideration of the reliability of each of the elements constituting the drive circuit.